Many devices include synchronous clock dividers that serve to divide and redistribute a clock signal within a logic circuit. High speed telecommunication devices, for example, make use of different clock signals that are produced by dividing an original clock signal. In particular, clock divider circuits reduce the frequency of an original clock signal. Ideally, the clock signals should be redistributed synchronously throughout a logic circuit so that the rising and falling edges of the original clock signal and the divided clock signals are perfectly aligned with one another.
Unfortunately, the divided clock signals are typically delayed with respect to the original clock signal. In particular, the divided clock signals are launched from flip-flops using the original clock signal. The flip-flops produce an internal delay from the clock input to the Q output, i.e., a “clock-to-Q” delay. The clock-to-Q delay causes differences in propagation delay between the original clock signal and the divided clock signal. Propagation delay differences prevent proper synchronization of the divided clock signals and the redistributed clock signal, undermining proper operation of the logic circuit.